ARM920T (TM) Core-based Microcontroller Provides Bandwidth

ARM920T (TM) Core-based Microcontroller Provides Bandwidth, Connectivity and Storage for GPS Host Processor Applications

Author:

Peter Bishop, Communications

Manager, Atmel, Rousset

Synopsis:

Atmel’s AT91RM9200 microcontroller combines an embedded ARM920T™ processor core with a rich set of system and application peripherals for connectivity, communications, data storage and control. These can be fully exploited by a state-of-the-art operating system such as INTEGRITY™ from Green Hills Software to provide a platform that is ideal for high-bandwidth, fine-grain multitasking applications such as the host processor for a Global Positioning System (GPS) navigation or telematics system. The integrated power management controller enables this performance to be delivered at minimal power consumption, a consideration of prime importance in hand-held or vehicle-mounted systems.

AT91RM9200 Architecture

The AT91RM9200 is built around an ARM920T processor core that attains more than 200 MIPS thanks to its Harvard architecture with separate instruction and data cache memories and buses, and pipelined instruction processing flow. A feature of prime interest to high-performance multitasking

applications is the Memory Management Unit (MMU). The MMU supports a 4-gigabyte virtual address space common to the core and peripherals. It provides address translation and access permission at a physical level. These facilities are exploited by the operating system

at an object level to provide guaranteed, protected memory areas and a deterministic

response to critical events. The Multiple-master Memory Controller (MMC) enables devices other than the ARM920T core to become memory masters. This makes most efficient use of the

throughput of the memory address and data buses and reduces the processor overhead during memory transfers. To complement the on-chip RAM and ROM, the External Bus Interface (EBI) provides direct communication to a variety of off-chip memories and memory cards including

Flash, SDRAM, CompactFlash® and SmartMedia™. This flexible combination allows the memory architecture of the system to be optimized for the application. A system peripheral of significance to realtime applications is Atmel’s proprietary Advanced Interrupt Controller (AIC). This transforms the basic two-level interrupt structure of the ARM920T core into an eight-level priority, individually maskable, vectored interrupt handling regime. An interrupt source is allocated to each AT91RM9200 peripheral device, as well as to eight external interrupt lines and to  software-sourced interrupts. Transfer of control to an interrupt handler is achieved in a few instruction cycles.

All AT91RM9200 peripherals are configured and controlled by a set of registers visible within the ARM920T address space. The various peripherals have a nearly-identical register structure for ease of programming. Software drivers are provided for all peripherals enabling most operations to be handled at an abstract level (and in a high-level language) by application code. Data transfer to and from the high-bandwidth peripherals is via the 20-channel Peripheral Data Controller (PDC) that provides a DMA function to keep processor overhead to a minimum during bulk data transfers. The peripheral set includes remote connectivity (USB V2.0 Host and Device), network connectivity (Ethernet 10/100 Base T MAC, PSTN phone line), local peripheral interfacing (Serial Peripheral Interface and Two-wire Interface), storage (DataFlash®, CompactFlash®, Multi-Media™ Card and SDCard™ Interface) and control (3-channel Synchronous Serial Controller, 6-channel Timer/Counter and Parallel I/Os). They enable the AT91RM9200 to be integrated seamlessly into a wide variety of high-performance applications. Power consumption by

the ARM920T core and entire peripheral set is regulated by the Power Management Controller that provides independent peripheral clock control (including a real-time clock) and implements an idle mode in which the processor clock is stopped until an interrupt is received.